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AT84CS001

5402AS–BDC–11/04

Description

The AT84CS001 is a monolithic high-speed demultiplexer (DMUX) using high-speed

Atmel technology.

It enables the user to lower a 10-bit stream of 2.2 Gsps maximum by a factor of two or

four. One can obtain a 1:8 ratio by using two interleaved AT84CS001 devices. The max-

imum input data rate is 2.2 Gsps in both 1:2 and 1:4 ratios.

The AT84CS001 DMUX is capable of processing an 11-bit data flow. The additional

11th bit (IOR/IORN) may be connected for example to the out-of-range bit of a 10-bit

ADC.

The input and output clocks as well as the input and output data are LVDS-compatible.

Digital inputs are 100

Ω differentially terminated on chip. Digital output buffers shall be

terminated by a 100

Ω differential ASIC load.

The improved architecture of the DMUX facilitates interfacing with high-speed ADCs

operating at up to 2.2 Gsps. No tuning of the delay between the data and clock paths

should be necessary since the data and clock paths are internally matched over the fre-

quency and specified temperature range.

However, in the case of misalignment or skews between the external clock path and the

data path, a fine delay tuning cell has been provided. Tuning may be requested for rates

exceeding 2 GHz, where the data skews are more sensitive. This tunable delay cell is

integrated in serial with the clock input. The delay is controlled by means of the CLK-

DACTRL analog control input. The tunable delay ranges from -250 ps to 250 ps for

CLKDACTRL varying from V

Two modes can be selected for the clock input (CLK and CLK/2) and the clock output

(DR and DR/2):

•

CLK and DR mode: only the rising edges of the input (CLK,CLKN) and output (DR,

DRN) clocks are active. The input (or output) clock rate remains the same as the

input or output data rate.

•

CLK/2 and DR/2 mode: both the rising and falling edges of the input (CLK,CLKN)

and output (DR, DRN) clocks are active. The input (or output) clock rate is half the

input or output data rate.

The data outputs can be received at the DMUX output in two different modes:

•

Staggered: even and odd bits are output with half a data period delay

•

Simultaneous: even and odd bits are output at the same time

The AT84CS001 DMUX is started by the ASYNCRST control input that acts as a master

asynchronous reset for the device. Once resetted, there is no loss of synchronization

over an indefinite time period, therefore no additional incoming synchronous reset signal

is required.

The power consumption of the AT84CS001 is 2.6W and can be reduced by approxi-

mately 60% of its nominal value by means of the SLEEP control input.

A standalone delay cell is provided. It features a typical 500 ps tuning range (± 250 ps

around the center value of DACTRL analog control input).

A Built-in Self Test (BIST) is implemented for rapid debugging of the DMUX.

Die junction temperature monitoring is possible by sensing the voltage drop across a

diode implemented close to the die’s hot point after forcing a 1 mA bias current.

The AT84CS001 DMUX is a companion chip designed to fit perfectly with all of Atmel’s

high-speed ADCs.