9

PS8641

10/14/04

PI90SD1636A

SERDES Gigabit Ethernet Transceiver

Symbol

Parameter

Min.

Typ.

Max.

Unit

Bit Sync Time

2500

bits

f_lock

Frequency Lock at Powerup

500

µ

s

Data Setup Before Rising Edge of RX_CLK

2.5

ns

Data Hold After Rising Edge of RX_CLK

1.5

RX_CLK Duty Cycle

40

60

%

RX_CLK Skew

7.5

8.5

ns

Receiver Latency

22.4

ns

28.0

bits

DATA

DATA

DATA

TX<9:0>

TX_CLK

1.4V

2.0V

0.8V

DATA

DATA

Figure 3. Transmitter Section Timing

T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5

DATA BYTE A

DATA BYTE B

DATA BYTE B

DATA BYTE C

1.4V

DOUT±

TX<9:0>

TX_CLK

t_TXLAT

Figure 4. Transmitter Latency

Notes:

1. This is the recovery for input phase jumps.

2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the

first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or

RBC0).