MPC866P datasheet(36/92 Pages) FREESCALE

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MPC866/859 Hardware Speciﬁcations

MOTOROLA

Bus Signal Timing

Table 10 shows the interrupt timing for the MPC866/859.

Figure 25 shows the interrupt detection timing for the external level-sensitive lines.

Figure 25. Interrupt Detection Timing for External Level Sensitive Lines

Figure 26 shows the interrupt detection timing for the external edge-sensitive lines.

Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines

Table 10. Interrupt Timing

Num

Characteristic 1

1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being deﬁned as

level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference

to the CLKOUT.

The timings I41, I42, and I43 are speciﬁed to allow the correct function of the IRQ lines detection circuitry, and has

no direct relation with the total system interrupt latency that the MPC866/859 is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (setup time)

6.00

—

I40

IRQx hold time after CLKOUT

2.00

—

I41

IRQx pulse width low

3.00

—

I42

IRQx pulse width high

3.00

—

I43

IRQx edge-to-edge time

4xTCLOCKOUT

——

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41

I42

I43

Freescale Semiconductor, Inc.

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