GS3471 datasheet(90/179 Pages) SEMTECH

90 / 179 page

GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

90 of 179

Semtech

www.semtech.com

4.21.4 Error Reporting

4.21.4.1 Data Block Number Error

When the 1 to 255d count sequence in the Data Block Number (DBN) word of Group A

audio data packets is discontinuous, the DBNA_ERR bit in the host interface

ACS_DET(HD/3G) or DBN_ERR(SD) register is set HIGH. When the 1 to 255 count

sequence in the DBN word of Group B audio data packets is discontinuous, the

DBNB_ERR bit in the ACS_DET(HD/3G) or DBN_ERR(SD) register is set HIGH.

The DBNA_ERR and DBNB_ERR flags also have associated INT_ENABLE[2] register

flags for configuration of error reporting in the Receiver. The DBNA_ERR and

DBNB_ERR flags remains set until cleared by writing to these locations.

4.21.4.2 ECC Error

The GS3471 monitors the ECC error status of the two selected audio groups, as

described in Section 4.21.2.6.

The ECC[B:A]_ERROR flags also have associated AUD_DET2 register flags for

configuration of error reporting in the Receiver. The ECC[B:A]_ERROR flags remain set

until written via the host interface.

Note: Low latency mode option is not available when ECC error is enabled.

4.22 GSPI - HOST Interface

The GS3471 is controlled via the Gennum Serial Peripheral Interface (GSPI).

The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data

output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK pin).

The GS3471 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the

application host processor.

All read and write access to the device is initiated and terminated by the application

host processor.

Please refer to GS3471 Host Interface Register Map for a detailed description of the CSR

registers available in the GS3471.

GS3471 Datasheet(PDF) 90 Page - Semtech Corporation