D17133CS datasheet(13/289 Pages) NEC

13 / 289 page

– viii –

LIST OF FIGURES (2/2)

Figure No.

Title

Page

13-1

Configuration of the 8-bit Timer Counter ...............................................................................

118

13-2

Timer Mode Register .............................................................................................................

119

13-3

Setting the Count Value in a Modulo Register .......................................................................

122

13-4

Error in Zero-Clearing the Count Registe during Counting ....................................................

124

13-5

Error in Starting Counting from the Count Halt State ............................................................

125

13-6

Reading 8-Bit Counter Count Values .....................................................................................

127

13-7

Timer Output Control Mode Register ....................................................................................

129

13-8

Configuration of Comparator .................................................................................................

131

13-9

Comparator Input Channel Selection Register .......................................................................

133

13-10

Reference Voltage Selection Register ...................................................................................

133

13-11

Comparator Operation Control Register ................................................................................

134

13-12

Block Diagram of the Serial Interface ....................................................................................

136

13-13

Timing of 8-Bit Transmission and Reception Mode

(Simultaneous Transmission Reception) ................................................................................

137

13-14

Timing of the 8-Bit Reception Mode .....................................................................................

138

13-15

Serial Interface Control Register ............................................................................................

139

13-16

Setting a Value in the Shift Register ......................................................................................

141

13-17

Reading a Value from the Shift Register ................................................................................

142

14-1

Interrupt Control Register ......................................................................................................

148

14-2

Interrupt Handling Procedure .................................................................................................

153

14-3

Return from Interrupt Handling ..............................................................................................

154

14-4

Interrupt Acceptance Timing Chart (when INTE=1 and IP

×××=1) .........................................

155

15-1

Cancellation of HALT Mode ...................................................................................................

164

15-2

Cancellation of STOP Mode ...................................................................................................

168

16-1

Reset Block Configuration .....................................................................................................

172

16-2

Resetting ...............................................................................................................................

172

16-3

Example of the Power-On Reset Operation ..........................................................................

175

16-4

Example of the Power-Down Reset Operation .....................................................................

177

16-5

Example of Reset Operation during the Period from Power-Down Reset to

Power Recovery ....................................................................................................................

178

17-1

Procedure of program Memory Writing .................................................................................

182

17-2

Procedure of Program Memory Reading ...............................................................................

183

19-1

Configuration of Control Register (

µPD17120, 17121) ..........................................................

258

19-2

Configuration of Control Register (

µPD17132, 17133, 17P132, 17P133) ..............................

264

C-1

Externally Installed System Clock Oscillation Circuit .............................................................

271

C-2

Unsatisfactory Oscillation Circuit Examples ..........................................................................

272

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