LM2502 datasheet(4/27 Pages) NSC

4 / 27 page

Pin Descriptions

Pin Name

No.

of Pins

I/O, Type

Description

Master (SER)

Slave (DES)

MPL SERIAL BUS PINS

MD[1:0]

IO, MPL

MPL Data Line Driver/Receiver

MPL Data Receiver/Line Driver

IO, MPL

MPL Clock Line Driver

MPL Clock Receiver

SSA

Ground

MPL Ground - see Power/Ground Pins

CONFIGURATION/PARALLEL BUS PINS

M/S*

LVCMOS

Master/Slave* Input,

M/S* = H for Master

Master/Slave* Input

M/S* = L for Slave

PD*

LVCMOS

Power_Down* Input,

H = Active

L = Power Down Mode

Power_Down* Input,

H = Active

L = Power Down Mode

MF0

(E or RD*)

IO,

LVCMOS

Multi-function Input Zero (0):

If MODE = L (m68 mode), E input pin,

data is latched on E High-to-Low

transition or E may be static High and

Data is latched on CS* Low-to-High edge

If MODE = H (i80 mode), Read Enable

input pin, active low. Read data is driven

when both RD* and CS* are Low.

Multi-function Output Zero (0):

If MODE = L (m68 mode),

E output pin, static High.

If MODE = H (i80 mode),

Read Enable output pin, active Low.

MF1

(R/W* or

WR*)

IO,

LVCMOS

Multi-function Input One (1):

If Mode = L (m68 mode), Read/Write*

pin, Read High, Write* Low

If Mode = H (i80 mode), Write* enable

input pin, active Low. Write data is

latched on the Low-to-High transition of

either WR* or CS* (which ever occurs

first).

Multi-function Output One (1):

If Mode = L (m68 mode)

Read/Write* pin,

Read High, Write* Low

If Mode = H (i80 mode)

Write* enable output pin, active Low.

CS1*

IO,

LVCMOS

ChipSelect1* – Input

H = Ignored

L = Active

ChipSelect1* – Output

H = Ignored

L = Active

CS2*

IO,

LVCMOS

ChipSelect2* – Input

H = Ignored

L = Active

ChipSelect2* – Output

H = Ignored

L = Active

A/D (RS or

A0)

IO,

LVCMOS

Address/Data – Input

H = Data

L = Address (Command)

Address/Data – Output

H = Data

L = Address (Command)

D[15:0]

IO,

LVCMOS

Data Bus – Inputs/Outputs

Data Bus – Outputs/Inputs

INTR

CLKDIS*

O or I,

LVCMOS

INTR is asserted when the read data is

ready and de-asserted upon a second

CPU Read cycle.

Clock Disable - CLKDIS*:

H = CLK output ON

L = CLK output LOW, allows for the

Slave clock output to be held static if not

used.

CLK

IO,

LVCMOS

Clock Input

Clock Output (Frequency Reference) –

no phase relationship to data – frequency

reference only.

Mode

LVCMOS

Mode Input Pin

H = i80 Mode,

L = m68 Mode

Mode Input Pin

H = i80 Mode,

L = m68 Mode

PLL_CON

[2:0]

3I,

LVCMOS

PLL Configuration Input Pins – see Table

Clock Divisor Configuration Input Pins –

see Table 10

LM2502 Datasheet(PDF) 4 Page - National Semiconductor (TI)

LM2502 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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