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LS1021A Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc |
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LS1021A Datasheet(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 71 page ![]() Architecture TWR-LS1021A Reference Manual, Rev. 0 Freescale Semiconductor 2-21 2.15 SPI interface The LS1021A / LS1020A serial peripheral interface (SPI) pins may be used for off-board SPI device access: For various SPI memory devices or SPI controller of various TWR modules. Figure 2-16 shows the overall connections of the two SPI portions. Figure 2-15. SPI architecture 2.15.1 SPI configuration and setup CPLD registers and SW selects SPI2 or LCD/LPUART and SPI1 or IFC. I2C1 0x2C USB HUB USB5534B Default this device is not connected to I2C1 bus. I2C1 - miniPCIe2 Slot Slave address depends on miniPCIe cards on the slot. I2C3 0x66, 0x67 CPU Core DCDC monitor LTC2945 n/a I2C3 - TWR-ELEV Pin NO. A7, A8 Slave address depends on TWR modules on the ELEV. Note: “7b” addresses do not include the R/W bit as an address member, though some datasheets might do so. For consistency, all I2C addresses are 7 bits of address only. Table 2-14. I2C bus device map (continued) I2C Bus 7b Addr. Description Device Notes |
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