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LPC47M14X Datasheet(PDF) 108 Page - SMSC Corporation |
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LPC47M14X Datasheet(HTML) 108 Page - SMSC Corporation |
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108 / 205 page  SMSC DS – LPC47M14X Page 108 Rev. 03/19/2001 6.13.9 Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. FIGURE 6 – KEYBOARD LATCH 8042 VCC DQ MINT MINT new RD 60 CLR MLATCH Bit FIGURE 7 – MOUSE LATCH The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0. These bits are defined as follows: Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default), 1=KINT is the latched 8042 KINT. See the “Configuration” section for a description of this register. 8042 VCC D Q KINT KINT new RD 60 CLR KLATCH Bit |
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