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CY26114 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY26114
Description  One-PLL Clock Generator
PDF  5 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY26114 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY26114
Document #: 38-07098 Rev. *A
Page 3 of 5
DC Electrical Characteristics
AC Electrical Characteristics
Parameter[2]
Name
Description
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD/VDDL = 3.3V
12
24
mA
IOL
Output Low Current
VOL = 0.5, VDD/VDDL = 3.3V
12
24
mA
IOH
Output High Current
VOH = VDDL – 0.5, VDDL=2.5V
8
16
mA
IOL
Output Low Current
VOL = 0.5, VDDL = 2.5V
8
16
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0.3
VDD
IVDD
Supply Current
AVDD/VDD Current
25
mA
IVDDL
Supply Current
VDDL Current (VDDL = 3.6V)
20
mA
IVDDL
Supply Current
VDDL Current (VDDL = 2.625V)
15
mA
Parameter[2]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1; t1/t2, 50% of
VDD
45
50
55
%
t3
Rising Edge Rate
Output Clock Rise Time, 20% – 80% of
VDD/VDDL = 3.3V
0.8
1.4
V/ns
t3
Rising Edge Rate
Output Clock Rise Time, 20% – 80% of
VDDL = 2.5V
0.6
1.2
V/ns
t4
Falling Edge Rate
Output Clock Fall Time, 80% – 20% of
VDD/VDDL = 3.3V
0.8
1.4
V/ns
t4
Falling Edge Rate
Output Clock Fall Time, 80% – 20% of
VDDL = 2.5V
0.6
1.2
V/ns
t5
Skew
Delay between related outputs at rising edge
250
ps
t9
Clock Jitter
Peak to Peak period jitter
200
ps
t10
PLL Lock Time
3ms
Figure 1. Duty Cycle Definitions: DC = t2/t1.
Figure 2. Rise Time and Fall Time Definitions.
Note:
2.
Not 100% tested.
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4



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