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CS6403 Datasheet(PDF) 22 Page - Cirrus Logic |
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CS6403 Datasheet(HTML) 22 Page - Cirrus Logic |
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22 / 54 page  Register SSI_CR2 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 PDC PDSD MGD res res res res res AV3 AV2 AV1 AV0 00 00 00 00 00 00 This register is cleared at Reset by the SSI. This register is read/written by the CPU every sample time. BIT NAME VALUE FUNCTION PDC Power Down Codec 0 R 1 Normal operation. The entire codec is powered down. PDSD Power Down Speaker Driver 0 R 1 Normal operation. Only the speaker driver in the codec is powered down. MGD Microphone 26 dB Gain Disable 0 R 1 Normal operation. The 26 dB microphone preamp is bypassed. res Reserved for test 00000 R Must be 00000. AV3-AV0 ADC Volume 0000 R . . 1111 ADC volume control is implemented in the CPU, with the attenuation being -3 dB times the ADC-volume value. "R" indicates value after Reset CS6403 22 DS192PP6 |
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