VC1

VC2

VSS

19

BQ28Z610-R1

www.ti.com

SLUSE07 – JANUARY 2020

Product Folder Links: BQ28Z610-R1

Submit Documentation Feedback

Copyright © 2020, Texas Instruments Incorporated

Feature Description (continued)

CAUTION

If the device is configured as a single-master architecture (an application processor)

and an occasional NACK is detected in the operation, the master can resend the

transaction. However, in a multi-master architecture, an incorrect ACK leading to

accidental loss of bus arbitration can cause a master to wait incorrectly for another

master to clear the bus. If this master does not get a bus-free signal, then it must have

in place a method to look for the bus and assume it is free after some period of time.

Also, if possible, set the clock speed to be 100 kHz or less to significantly reduce the

issue described above for multi-mode operation.

device were holding the lines, releasing them frees the master to drive the lines. Note: that the low time setting

can be under firmware control but the HW default is 2 seconds.

8.3.13 Cell Balancing Support

The integrated cell balancing FETs included in the BQ28Z610-R1 device enable the AFE to bypass cell current

around a given cell or numerous cells to effectively balance the entire battery stack. External series resistors

placed between the cell connections and the VCx input pins set the balancing current magnitude. The cell

balancing circuitry can be enabled or disabled via the CELL_BAL_DET[CB2, CB1] control register. Series input

resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.

Figure 20. Internal Cell Balancing

8.3.14 N-Channel Protection FET Drive

The BQ28Z610-R1 device controls two external N-Channel MOSFETs in a back-to-back configuration for battery

protection. The charge (CHG) and discharge (DSG) FETs are automatically disabled if a safety fault (AOLD,

ASSC, ASCD, SOV) is detected, and can also be manually turned off using AFE_CONTROL[CHGEN, DSGEN]

= 0, 0. When the gate drive is disabled, an internal circuit discharges CHG to VC2 and DSG to PACK.

8.3.15 Low Frequency Oscillator

The BQ28Z610-R1 AFE includes a low frequency oscillator (LFO) running at 262.144 kHz. The AFE monitors the

LFO frequency and indicates a failure via LATCH_STATUS[LFO] if the output frequency is much lower than

normal.

8.3.16 High Frequency Oscillator

The BQ28Z610-R1 AGG includes a high frequency oscillator (HFO) running at 16.78 MHz. It is synthesized from

the LFO output and scaled down to 8.388 MHz with 50% duty cycle.