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AM6548 Datasheet(PDF) 1 Page - Texas Instruments |
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AM6548 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 277 page  Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 AM654x, AM652x Sitara™ Processors Silicon Revision 1.0 1 Device Overview 1 1.1 Features 1 Processor cores: • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz – Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED – Each A53 core has 32KB L1 ICache and 32K L1 DCache • Dual-core Arm® Cortex®-R5F at up to 400 MHz – Supports lockstep mode – 16KB ICache, 16KB DCache, and 64KB RAM per R5F core Industrial subsystem: • Three gigabit Industrial Communication Subsystems (PRU_ICSSG) – Up to two 10/100/1000 Ethernet ports per PRU_ICSSG – Supports two SGMII ports (2) – Compatibility with 10/100Mb PRU-ICSS – 24× PWMs per PRU_ICSSG – Cycle-by-cycle control – Enhanced trip control – 18× Sigma-delta filters per PRU_ICSSG – Short circuit logic – Over-current logic – 6× Multi-protocol position encoder interfaces per PRU_ICSSG Memory subsystem: • Up to 2MB of on-chip L3 RAM with SECDED • Multi-core Shared Memory Controller (MSMC) – Up to 2MB (2 banks × 1MB) SRAM with SECDED – Shared coherent Level 2 or Level 3 memory- mapped SRAM – Shared coherent Level 3 Cache – 256-bit processor port bus and 40-bit physical address bus – Coherent unified bi-directional interfaces to connect to processors or device masters – L2, L3 Cache pre-warming and post flushing – Bandwidth management with starvation bound – One infrastructure master interface – Single external memory master interface – Supports distributed virtual system – Supports internal DMA engine – Data Routing Unit (DRU) – ECC error protection • DDR Subsystem (DDRSS) – Supports DDR3L/DDR4 memory types up to DDR-1600 – Supports LPDDR4 memory type up to DDR- 1333 – 32-bit data bus and 7-bit SECDED bus – 32GB of total addressable space • General-Purpose Memory Controller (GPMC) SafeTI™ semiconductor component: • Designed for functional safety applications • Developed according to the requirements of IEC 61508 • Achieves systematic integrity of SIL-3 • For the MCU safety island, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2 • For the rest of the SoC, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2 • In addition, sufficient architectural metrics are in place to achieve execution of SIL-3 applications given a proper safety concept (for example reciprocal comparison by software) • Functional safety manual available • Safety-related certification – Component level functional safety certification by TÜV SÜD [certification in progress] • Functional safety features: – ECC or parity on calculation-critical memories and internal bus interconnect – Firewalls to help provide Freedom From Interference (FFI) – Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM – Hardware error injection support for test-for- diagnostics – Error Signaling Modules (ESM) for capture of functional safety related errors – Voltage, temperature, and clock monitoring – Windowed and non-windowed watchdog timers in multiple clock domains • MCU island – Isolation of the dual-core Arm® Cortex®-R5F |
Similar Part No. - AM6548_V01 |
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Similar Description - AM6548_V01 |
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