7 / 51 page
SMH4046
Preliminary Information
Summit Microelectronics, Inc
2082 1.7 08/23/04
7
Symbol
Pin
Type
Description
CARD_12V
39
I
12V card side supply input. This input is monitored for power integrity. If it falls
below the 12V sense threshold, the CARD_V_VLD signal is de-asserted.
VCC12
40
I
Bus-side 12V input
VCC5V (VDD)
41
PWR
This pin supplies power to the SMH4046 and is monitored for power integrity.
FPGA_NSTS
42
I
FPGA configuration status input pin
FPGA_CFGD
ONE
43
I
FPGA_CFGDONE indicates completion of the configuration process.
FPGA_NCFG
44
O
FPGA_NCFG is a configuration control output. A low transition resets the target
device; a low-to-high transition begins configuration.
FPGA_DO
45
O
FPGA_DO provides preamble and configuration data to downstream devices in a
daisy-chain.
FPGA_DCLK
46
O
FPGA Configuration clock output. Clock output used to clock configuration data
using pin FPGA_DO.
NC
47
NC
No Connect
SDA
48
I/O
The bidirectional I
2C serial data line.
PIN DESCRIPTIONS (CONTINUED)
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
