PCF2127TSLASH2Y datasheet(67/100 Pages) PHILIPS

67 / 100 page

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

67 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

9.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is illustrated in Figure 43.

9.2.5 I2C-bus protocol

After a start condition, a valid hardware address has to be sent to a PCF2127 device. The

appropriate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte is

shown in Table 88.

Fig 42. System configuration

Fig 43. Acknowledgement on the I2C-bus

PCF2127T/2Y Datasheet(PDF) 67 Page - NXP Semiconductors