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STM8S Datasheet(PDF) 95 Page - STMicroelectronics |
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STM8S Datasheet(HTML) 95 Page - STMicroelectronics |
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95 / 467 page  DocID14587 Rev 14 95/467 RM0016 Clock control (CLK) 104 9.9.7 Peripheral clock gating register 1 (CLK_PCKENR1) Address offset: 0x07 Reset value: 0xFF 7 654 3210 PCKEN1[7:0] rw rw rw rw rw rw rw rw Bits 7:0 PCKEN1[7:0]: Peripheral clock enable These bits are written by software to enable or disable the fMASTER clock to the corresponding peripheral (see Table 17). 0: fMASTER to peripheral disabled 1: fMASTER to peripheral enabled Table 17. Peripheral clock gating bits Control bit Peripheral PCKEN17 TIM1 PCKEN16 TIM3 PCKEN15 TIM2/TIM5 (product dependent) PCKEN14 TIM4/ TIM6 (product dependent) PCKEN13 UART1/2/3/4 (product dependent, see datasheet for bit assignment table) PCKEN12 PCKEN11 SPI PCKEN10 I2C |
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