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STM8S Datasheet(PDF) 315 Page - STMicroelectronics |
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STM8S Datasheet(HTML) 315 Page - STMicroelectronics |
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315 / 467 page ![]() DocID14587 Rev 14 315/467 RM0016 Inter-integrated circuit (I2C) interface 319 21.7.11 Clock control register low (I2C_CCRL) Address offset: 0x02 Reset value: 0x0B 7 654 3210 CCR[7:0] rw Bits 7:0 CCR[7:0] Clock control register (Master mode) Controls the SCLH clock in Master mode. – Standard mode: Period(I2C) = 2 * CCR * tMASTER thigh = CCR * tMASTER tlow = CCR * tMASTER – Fast mode: If DUTY = 0: Period(I2C) = 3* CCR * tMASTER thigh = CCR * tMASTER tlow = 2 * CCR * tMASTER If DUTY = 1: (to reach 400 kHz) Period(I2C) = 25 * CCR * tMASTER thigh = 9 * CCR * tMASTER tlow = 16 * CCR * tMASTER Note: tCK = 1/ fMASTER. fMASTER is the input clock to the peripheral configured using clock control register. The minimum allowed value is 04h, except in FAST DUTY mode where the minimum allowed value is 0x01. thigh = tr(SCL) + tw(SCLH). See device datasheet for the definitions of parameters. tlow = tf(SCL) + tw(SCLL). See device datasheet for the definitions of parameters. I2C communication speed, fSCL = 1/(thigh + tlow) The real frequency may differ due to the analog noise filter input delay. |
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