4

Pin Descriptions

PAD NUMBER

DESIGNATION

DESCRIPTION

1

VCMP

This is the input terminal from an external error amplifier. A MOS input voltage follower buffers

this terminal. The buffer output is the IRFO terminal. The external error amplifier may be either

an operational amplifier or a transconductance amplifier like the CA3080. This node may be used

for both gain and frequency compensation of the control loop.

This is the analog supply input. An external 12V supply is required.

Voltage input for the chip’s digital circuits.

4

FLLN

One pad of two clocking terminals. This terminal has an external 50

µA pull-up current that allows

will start wiith the falling edge of the CLCK input. With FLLN low or grounded, the DMOS ON

cycle will start on the rising edge of the CLCK input.

5

CLCK

The other clock input pad. An external clock is applied to this terminal. This terminal has no pull-

up current or resistance. See FLLN above for phasing information.

6

COOL

Over-temperature indication is provided at this pad. When the chip temperature is below the ther-

mal threshold, the open drain DMOS transistor is in the high impedance state. When the thermal

threshold is exceeded, COOL is held low.

7

TMON

This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By

able the thermal monitor function. Thermal threshold occurs at a nominal junction temperature

8

IRFO

A resistor placed between this pad and IRFI converts the VCMP signal to a reference current for

the current sense comparator. The cycle by cycle peak current is set by the value to this resistor

value of the external resistor in ohms. A maximum VCMP of 8V and a resistor of 1800

Ω will keep

the drain current below the absolute maximum specification of 20A.

9IRFI

See IRFO.

10

AGND

Analog ground.

11

DGND

Digital ground.

12 & 21

These pads are used to decouple the high current pulses to the output driver transistors. The

capacitor should be at least a 0.1

µF chip capacitor placed close to this pad and the DMOS

source pads.

13, 15, 17, 19

S

Source pads of the DMOS power transistor.

14, 16, 18, 20

D

Drain pads of the DMOS power transistor.

HIP5063