XRT83SL34 datasheet(39/80 Pages) EXAR

39 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every

transition of NLCD. The host has the option to ignore the request from the remote terminal, or to respond to the

request and manually activate Remote Loop-Back. The host can subsequently activate the detection of the

Loop-Down Code by setting NLCDE1=”1” and NLCDE0=”0”. In this case, receiving the “001” Loop-Down Code

for longer than 5 seconds will set the NLCD bit to “1” and if the NLCD interrupt is enabled, the chip will initiate

an interrupt on every transition of NLCD. The host can respond to the request from the remote terminal and

remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1=”0” and NLCDE0=”1”) and Loop-

Down (NLCDE1=”1” and NLCDE0=”0”) Code detection modes, the NLCD interface bit will be set to “1” upon

receiving the corresponding code in excess of 5 seconds in the receive data. The chip will initiate an interrupt

any time the status of the NLCD bit changes and the Network Loop-code interrupt is enabled.

In the Host mode, setting the interface bits NLCDE1=”1” and NLCDE0=”1” enables the automatic Loop-Code

detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to “110”. As this mode is

initiated, the state of the NLCD interface bit is reset to “0” and the chip is programmed to monitor the receive

input data for the Loop-Up Code. If the “00001” Network Loop-Up Code is detected in the receive data for

longer than 5 seconds in addition to the NLCD bit in the interface register being set, Remote Loop-Back is

automatically activated. The chip stays in remote Loop-Back even if it stops receiving the “00001” pattern. After

the chip detects the Loop-Up code, sets the NLCD bit and enters Remote Loop-Back, it automatically starts

monitoring the receive data for the Loop-Down code. In this mode however, the NLCD bit stays set even if the

receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote Loop-Back is still

in effect. Remote Loop-Back is removed if the chip detects the “001” Loop-Down code for longer than 5

seconds. Detecting the “001” code also results in resetting the NLCD interface bit and initiating an interrupt.

The Remote Loop-Back can also be removed by taking the chip out of the Automatic detection mode by

programming it to operate in a different state. The chip will not respond to remote Loop-Back request if Local

Analog Loop-Back is activated locally. When programmed in Automatic detection mode the NLCD interface bit

stays “High” for the whole time the Remote Loop-Back is activated and initiates an interrupt any time the status

of the NLCD bit changes provided the Network Loop-code interrupt is enabled.

TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)

Each channel of XRT83SL34 includes a QRSS pattern generation and detection block for diagnostic purposes

that can be activated only in the Host mode by setting the interface bits TXTEST2=”1”, TXTEST1=”0” and

TXTEST0=”0”. For T1 systems, the QRSS pattern is a 220-1pseudo-random bit sequence (PRBS) with no

more than 14 consecutive zeros. For E1 systems, the QRSS pattern is 215 -1 PRBS with an inverted output.

With QRSS and Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD

interface bit, all main functional blocks within the transceiver can be verified.

When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD

changes from “Low” to “High”. After pattern synchronization, any bit error will cause QRPD to go “Low” for one

clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.

With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the

INSBER interface bit from “0” to “1”. Bipolar violation can also be inserted either in the QRSS pattern, or input

data when operating in the single-rail mode by transitioning the INSBPV interface bit from “0” to “1”. The state

of INSBER and INSBPV bits are sampled on the rising edge of the TCLK_n. To insure the insertion of the bit

error or bipolar violation, a “0” should be written in these bit locations before writing a “1”.

XRT83SL34 Datasheet(PDF) 39 Page - Exar Corporation

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