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LP4059B6F Datasheet(PDF) 6 Page - Lowpower Semiconductor inc |
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LP4059B6F Datasheet(HTML) 6 Page - Lowpower Semiconductor inc |
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6 / 9 page ![]() LP4059-00 Jan.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 6 of 9 Preliminary Datasheet LP4059 Stability Considerations The constant-voltage mode feedback loop is stable without an output capacitor provided a battery is connected to the charger output. With no battery present, an output capacitor is recommended to reduce ripple voltage. When using high value, low ESR ceramic capacitors, it is recommended to add a 1Ω resistor in series with the capacitor. No series resistor is needed if tantalum capacitors are used. Manual Shutdown At any point in the charge cycle, the LP4059 can be put into shutdown mode by removing RPROG. This reduces the battery drain current to less than 1µA. A new charge cycle can be initiated by reconnecting the program resistor. The CHRG pin is in a high impedance state if the LP4059 is in under voltage lockout mode: either VCC is within 100mV of the BAT pin voltage or insufficient voltage is applied to the VCC pin. Automatic Recharge Once the charge cycle is terminated, the LP4059 continuously monitors the voltage on the BAT pin using a comparator with a 2ms filter time (tRECHRG). A charge cycle restarts when the battery voltage falls below 4.05V (which corresponds to approximately 80% to 90% battery capacity). This ensures that the battery is kept at or near a fully charged condition and eliminates the need for periodic charge cycle initiations. CHRG output enters a strong pull-down state during recharge cycles. Under voltage Lockout (UVLO) An internal under voltage lockout circuit monitors the input voltage and keeps the charger in shutdown mode until VCC rises above the under voltage lockout threshold .The UVLO circuit has a built-in hysteresis of 500mV. Furthermore, to protect against reverse current in the power MOSFET, the UVLO circuit keeps the charger in shutdown mode if VCC falls to within 30mV of the battery voltage. If the UVLO comparator is tripped, the charger will not come out of shutdown mode until VCC raises 100mV above the battery voltage. Power Dissipation(SOT23-5) The conditions that cause the LP4059 to reduce charge current through thermal feedback can be approximated by considering the power dissipated in the IC. Nearly all of this power dissipation is generated by the internal MOSFET—this is calculated to be approximately: PD=(VCC-VBAT)×IBAT Where PD is the power dissipated, VCC is the input supply voltage, VBAT is the battery voltage and IBAT is the charge current. The approximate ambient temperature at which the thermal feedback begins to protect the IC is: TA=150℃-PD×θJA TA=150℃-(VCC-VBAT)×IBAT×θJA VCC Bypass Capacitor Many types of capacitors can be used for input bypassing; however, caution must be exercised when using multilayer ceramic capacitors. Because of the self-resonant and high Q characteristics of some types of ceramic capacitors, high voltage transients can be generated under some start-up conditions, such as connecting the charger input to a live power source .Adding a 1.5Ω resistor in series with an X5R ceramic capacitor will minimize start-up voltage transients. Intelligent Charge Control The LP4059 includes an intelligent charge control logic(SLP) that is connected to BAT through a 1MΩ pull-up resistor. If the I/O interface connected to the SLP pin is in a high-impedance state, a charge cycle restarts when the battery voltage below 3.4V. When the battery voltage rises than 3.6V, the chip will stop charging. Controlling the SLP through an external I/O output signal can turn the chip on/off. When the SLP is in a low-level state, the chip will continue to charge. When the SLP is in a high-level or high-impedance state, chip enters standby mode. This reduces the battery drain current to less than 1μA and the supply current to less than 1μA. |
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