IS25LP032D-RGLA3 datasheet(81/118 Pages) ISSI

Part #	IS25LP032D-RGLA3

Description	SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	118 Pages

Scroll/Zoom	100%

Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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81 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.36 INFORMATION ROW ERASE OPERATION (IRER, 64h)

Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the

operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is

automatically reset after the completion of the operation.

The sequence of IRER operation: Pull CE# low to select the device  Send IRER instruction code  Send three

address bytes  Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE# is pulled

high, Erase operation will begin immediately. The internal control logic automatically handles the erase voltage and

timing.

Figure 8.60 IRER (Information Row Erase) Sequence

Instruction = 64h

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

IS25LP032D-RGLA3 Datasheet(PDF) 81 Page - Integrated Silicon Solution, Inc