PFS172 datasheet(68/92 Pages) PADAUK

68 / 92 page

PFS172

8bit MTP MCU with 8-bit ADC

Page 68 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

6.25. Timer2 Control Register (tm2c), IO address = 0x30

Bit

Reset

R/W

Description

7 - 4

0000

R/W

Timer2 clock selection.

0000 : disable

0001 : CLK

0010 : IHRC or IHRC *2 (by code option TMx_source)

0011 : EOSC

0100 : ILRC

0101 : comparator output (ICE does NOT support.)

1000 : PA0 (rising edge)

1001 : ~PA0 (falling edge)

1010 : PB0 (rising edge)

1011 : ~PB0 (falling edge)

1100 : PA4 (rising edge)

1101 : ~PA4 (falling edge)

Others: reserved

Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does

NOT be stopped, Timer2 will keep counting when ICE is in halt state.

3 - 2

R/W

Timer2 output selection.

00 : disable

01 : PB2

10 : PA3

11 : PB4

R/W

Timer2 mode selection.

0 / 1 : period mode / PWM mode

R/W

Enable to inverse the polarity of Timer2 output.

0 / 1: disable / enable

6.26. Timer2 Counter Register (tm2ct), IO address = 0x31

Bit

Reset

R/W

Description

7 - 0

0x00

R/W

Bit [7:0] of Timer2 counter register.

6.27. Timer2 Scalar Register (tm2s), IO address = 0x32

Bit

Reset

R/W

Description

PWM resolution selection.

0 : 8-bit

1 : 6-bit or 7-bit (by code option TMx_bit)

6 - 5

Timer2 clock pre-scalar.

00 : ÷ 1

01 : ÷ 4

10 : ÷ 16

11 : ÷ 64

4 - 0

00000

Timer2 clock scalar.

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