7.2

INT1_CTRL (21h)

INT1 pin control register

INT1_

DRDY

INT1_

BOOT

INT1_

OVR

INT1_ FSS5

INT1_FTH

INT1_ EXT

0 (1)

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

INT1_DRDY

Accelerometer data ready on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_ BOOT

Boot status available on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_OVR

Overrun flag on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_ FSS5

FSS5 full FIFO flag on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_FTH

FIFO threshold flag on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_ EXT

INT1 pin configuration. Default value: 0

It configures the INT1 pad as output for FIFO flags or as external asynchronous input trigger to FIFO.

INT2 pad is always available as output for FIFO flags.

(0: INT1 as output interrupt; 1: INT1 as input channel)

IIS3DHHC

INT1_CTRL (21h)

DS12292 - Rev 3

page 18/30