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ADAR2004 Datasheet(PDF) 5 Page - Analog Devices |
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ADAR2004 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 37 page  Data Sheet ADAR2004 Rev. 0 | Page 5 of 37 TIMING SPECIFICATIONS VPOS1, VPOS2, VPOS4 = 2.5 V, VPOS3 = VREG, and TA = −40°C to +85°C, unless otherwise noted. See Figure 2 to Figure 4 for the timing diagrams. Table 2. SPI Timing Parameter Description Test Conditions/Comments Min Typ Max Unit fSCLK Maximum clock rate Write only 40 MHz Write and read 15 MHz tPWH Minimum pulse width high 10 ns tPWL Minimum pulse width low 10 ns tDS Setup time, SDIO to SCLK 5 ns tDH Hold time, SDIO to SCLK 5 ns tDV Data valid, SDO to SCLK 5 ns tDCS Setup time, CS to SCLK 10 ns tR SDIO, SDO rise time Outputs loaded with 10 pF, 10% to 90% 40 ns tF SDIO, SDO fall time Outputs loaded with 10 pF, 10% to 90% 40 ns Timing Diagrams DON’T CARE DON’T CARE SDIO SCLK DON’T CARE DON’T CARE R/W CS A14 A13 INSTRUCTION CYCLE DATA TRANSFER CYCLE A2 A1 A0 D7 D6 D5 D2 D1 D0 Figure 2. SPI Transaction Structure (MSB First) DON’T CARE DON’T CARE DON’T CARE DON’T CARE SDIO SCLK CS WRITE A14 A13 A2 tDS tPWL tPWH tDCS tDH A1 A0 D7 D6 D5 D2 D1 D0 Figure 3. SPI Write Timing Diagram DON’T CARE DON’T CARE DON’T CARE DON’T CARE SDIO SDO SCLK CS READ A14 A13 A2 tR tDV tF A1 A0 DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE D7 D6 D5 D1 D0 Figure 4. SPI 4-Wire Read Timing Diagram |
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