RA4M3 datasheet(6/92 Pages) RENESAS

6 / 92 page

1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the

features.

Memory

1 MB code flash

8 KB data flash

128 KB SRAM

DMA

DMAC × 8

System

Mode control

Power control

protection

MOSC/SOSC

Clocks

(H/M/L) OCO

PLL/PLL2

Battery backup

GPT32 x 4

GPT16 x 4

Timers

AGT × 6

RTC

CTSU

Arm Cortex-M33

DTC

CAC

POR/LVD

Reset

Human machine interfaces

ELC

Event link

SCE9

Security

Analog

CRC

Data processing

DOC

Communication interfaces

QSPI

IIC × 2

SDHI

SPI

CAN × 2

SSIE

USBFS

SCI × 6

TSN

DAC12 × 2

ADC12 × 2

1 KB Standby

SRAM

Bus

MPU

ICU

WDT/IWDT

MPU

NVIC

System timer

Test and DBG interface

IDAU

DSP

FPU

Note:

Not available on all parts.

Figure 1.1

Block diagram

1.3

Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a

list of products.

RA4M3 Datasheet

1. Overview

R01DS0368EJ0120 Rev.1.20

Dec 2, 2020

Page 6 of 92

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