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BLUENRG-LP Datasheet(PDF) 5 Page - STMicroelectronics |
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BLUENRG-LP Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 72 page  1 Functional overview 1.1 System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Three masters: – CPU (Cortex®-M0+) core S-bus – DMA1 – Radio system • Nine slaves: – Internal Flash memory on CPU (Cortex®-M0+) S bus – Internal SRAM0 (16 kB) – Internal SRAM1 (16 kB) – Internal SRAM2 (16 kB) – Internal SRAM3 (16 kB) – APB0 peripherals (through an AHB to APB bridge) – APB1 peripherals (through an AHB to APB bridge) – AHB0 peripherals – AHBRF including AHB to APB bridge and radio peripherals (connected to APB2) The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. BlueNRG-LP Functional overview DS13282 - Rev 2 page 5/72 |
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