7

Application information

7.1

External capacitors

The STLQ020 voltage regulator requires external low ESR capacitors to assure the control loop stability. These

capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance

defined in the following chapters. Input and output capacitors should be located as close as possible to the

relevant pins.

Input capacitor

An input capacitor, with a minimum value of 1 μF, must be located as close as possible to the input pin of the

device and returned to a clean analog ground. A good quality, low-ESR ceramic capacitor is suggested. It helps to

ensure stability of the control loop, reduces the effects of inductive sources and improves ripple rejection.

Capacitance higher than 1 µF can be chosen in case of fast load transients in application.

Output capacitor

STLQ020 requires a low-ESR capacitor connected on its output, to keep the control loop stable and reduce the

risk of ringing and oscillations. The control loop is designed to be stable with any good quality ceramic capacitor

(such as X5R/X7R types) with a minimum value of 1 µF and equivalent series resistance in the [3 – 500 mΩ]

range. It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable

region over the full operating temperature, load and input voltage ranges, to assure stability. Therefore,

capacitance and ESR variations must be taken into account in the design phase to ensure the device works in the

expected stability region. There is no maximum limit to the output capacitance, provided that the above conditions

are respected.

7.2

Output voltage adjustment (adjustable version)

In the adjustable version, available on the DFN6-2x2 and SOT323-5L packages, the output voltage can be

the internal power pass element, by connecting a resistor divider between the ADJ pin and the output, allowing

the remote voltage sensing.

The resistor divider should be selected using the following equation:

Equation 1

For best accuracy and stability the resistor divider should be designed in order to allow that a current of at least

500 nA flows across it. The current flowing into the ADJ pin is typically less than 1 nA, therefore causing negligible

change in final the output voltage.

7.3

Enable pin operation

This is a logic control pin, CMOS level-compatible, which can be used to turn On/Off the regulator.It is active high,

so when it is pulled down, the device enters the shutdown mode, drastically reducing the current consumption, to

less just few nA.

Since it is not internally pulled-up, when the enable feature is not used, this pin must not be left floating. It can be

To assure reliable operation, the signal source used to drive the EN pin, must be able to swing above and below

7.4

Power dissipation

A proper PCB design is recommended, to ensure that the device internal junction temperature is kept below

125°C, in all the operating condition.

Depending on the package option, the thermal energy generated by the device flows from the die surface to the

PCB copper area through the package leads, solder bumps and/or exposed pad.

STLQ020

Application information

DS12072 - Rev 3

page 13/31