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STM32L021D4 Datasheet(PDF) 112 Page - STMicroelectronics |
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STM32L021D4 Datasheet(HTML) 112 Page - STMicroelectronics |
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112 / 114 page ![]() Revision history STM32L021x4 112/114 DocID027982 Rev 5 20-Jun-2016 4 Updated: – Features in cover page: Stop mode values, number of DMA channels, number of I/Os, number of communication peripherals. – Table 26: Current consumption in Low-power Run mode, Table 27: Current consumption in Low-power Sleep mode, Table 33: Low-power mode wakeup timings, Table 35: Low-speed external user clock characteristics 12-Sep-2017 5 Removed I/O operation from Table 2: Functionalities depending on the operating power supply range. Updated Section 3.4.4: Boot modes and added Note 7. in Table 12: Pin definitions. Changed USARTx_RTS and LPUARTx_RTS into USARTx_RTS_DE and LPUARTx_RTS_DE, respectively in Section 4: Pin descriptions. In Section 5: Memory mapping, replaced memory mapping schematic by reference to the reference manual. Updated introduction text in Section 6.2: Absolute maximum ratings to mention device mission profile and extended mission profiles. Added note in Table 48: I/O current injection susceptibility. Updated minimum and maximum values of I/O weak pull-up equivalent resistor (RPU) and weak pull-down equivalent resistor (RPD) in Table 49: I/O static characteristics. Updated minimum and maximum values of NRST weak pull-up equivalent resistor (RPU) in Table 52: NRST pin characteristics. Added note 2 related to the position of the external capacitor below Figure 25: Recommended NRST pin protection. Updated Section : I2C interface characteristics. Removed section USART/LPUART characteristics. Updated Figure 28: SPI timing diagram - slave mode and CPHA = 0, Figure 29: SPI timing diagram - slave mode and CPHA = 1(1) and Figure 30: SPI timing diagram - master mode(1). Table 75. Document revision history Date Revision Changes |
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