STM32L552CC_V01 datasheet(60/340 Pages) STMICROELECTRONICS

60 / 340 page

Functional overview

STM32L552xx

60/340

DS12737 Rev 6

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Three functional modes: indirect, status-polling, and memory-mapped

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Read and write support in memory-mapped mode

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Supports for single, dual, quad and octal communication

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Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two

quad memories in parallel.

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SDR and DTR support

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Data strobe support

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Fully programmable opcode for both indirect and memory mapped mode

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Fully programmable frame format for both indirect and memory mapped mode

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Each of the five following phases can be configured independently (enable, length,

single/dual/quad communication)

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Instruction phase

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Address phase

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Alternate bytes phase

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Dummy cycles phase

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Data phase

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HyperBusTM support

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Integrated FIFO for reception and transmission

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8, 16, and 32-bit data accesses are allowed

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DMA channel for indirect mode operations

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Timeout management

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Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.

Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a

granularity of 64 Kbytes.

The OCTOSPI registers can be configured as secure through the TZSC controller.

STM32L552CC Datasheet(PDF) 60 Page - STMicroelectronics

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