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STPMIC1APQR Datasheet(PDF) 108 Page - STMicroelectronics |
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STPMIC1APQR Datasheet(HTML) 108 Page - STMicroelectronics |
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108 / 140 page  6.5.10 Interrupt clear mask registers (INT_CLEAR_MASK_Rx) Table 57. INT_CLEAR_MASK_Rx Name Address 7 6 5 4 3 2 1 0 INT_CLEAR _MASK_R1 0xA0 SWOUT _RI SWOUT _FA VBUS OTG_RI VBUS OTG_FA WKP _RI WKP _FA PKEY _RI PKEY _FA INT_CLEAR _MASK_R2 0xA1 BST _OVP BST _OCP SWOUT _OCP VBUS OTG_OCP BUCK4_ OCP BUCK3_ OCP BUCK2_ OCP BUCK1_ OCP INT_CLEAR _MASK_R3 0xA2 SWOUT _SH VBUS OTG_SH LDO6_ OCP LDO5_ OCP LDO4_ OCP LDO3_ OCP LDO2_ OCP LDO1_ OCP INT_CLEAR _MASK_R4 0xA3 SWIN _RI SWIN _FA reserved reserved VINLOW _RI VINLOW _FA THW _RI THW _FA Address: 0xA0 – 0xA3 Type: write register - read x00 Default: 0x00 Description: interrupt clear registers. Registers are default on RSTn assertion. Writing 1 in the bit clears the mask of the corresponding interrupt in INT_MASK_Rx. Refer to Section 6.5.2 Interrupt pending register 1 (INT_PENDING_R1), Section 6.5.3 Interrupt pending register 2 (INT_PENDING_R2), Section 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) and Section 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) about the interrupt description. STPMIC1 Interrupt registers DS12792 - Rev 7 page 108/140 |
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