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STPMIC1APQR Datasheet(PDF) 105 Page - STMicroelectronics |
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STPMIC1APQR Datasheet(HTML) 105 Page - STMicroelectronics |
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105 / 140 page  6.5.7 Interrupt clear registers (INT_CLEAR_Rx) Table 54. INT_CLEAR_Rx Name Address 7 6 5 4 3 2 1 0 INT _CLEAR_R1 0x70 SWOUT _RI SWOUT _FA VBUSOTG _RI VBUSOTG _FA WKP _RI WKP _FA PKEY _RI PKEY _FA INT _CLEAR_R2 0x71 BST _OVP BST _OCP SWOUT _OCP VBUSOTG _OCP BUCK4 _OCP BUCK3 _OCP BUCK2 _OCP BUCK1 _OCP INT _CLEAR_R3 0x72 SWOUT _SH VBUSOTG _SH LDO6_ OCP LDO5 _OCP LDO4 _OCP LDO3 _OCP LDO2 _OCP LDO1 _OCP INT _CLEAR_R4 0x73 SWIN _RI SWIN _FA reserved reserved VINLOW _RI VINLOW _FA THW _RI THW _FA Address: 0x70-0x73 Type: write register - read x00 Default: 0x00 Description: Interrupt clear registers. Write registers only. Read always return 0x00. Writing 1 clears the corresponding interrupt event in INT_PENDING_Rx Refer to Section 6.5.2 Interrupt pending register 1 (INT_PENDING_R1), Section 6.5.3 Interrupt pending register 2 (INT_PENDING_R2), Section 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) and Section 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) about the interrupt description. STPMIC1 Interrupt registers DS12792 - Rev 7 page 105/140 |
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