ADP7118ACPZN2.5-R7 datasheet(22/24 Pages) AD

22 / 24 page

ADP7118

Data Sheet

Rev. F | Page 22 of 24

OUTLINE DIMENSIONS

1.70

1.60

1.50

0.425

0.350

0.275

TOP VIEW

0.35

0.30

0.25

BOTTOM VIE W

PIN 1 INDEX

AREA

0.60

0.55

0.50

1.10

1.00

0.90

0.20 REF

0.05 MAX

0.02 NOM

0.65 BSC

EXPOSED

PAD

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

2.10

2.00 SQ

1.90

0.15 MIN

SEATING

PLANE

P IN 1

IN D IC ATO R AR E A OP T IO N S

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP]

2.00 mm × 2.00 mm Body and 0.55 mm Package Height

(CP-6-3)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-012-A A

1.27

0.40

1.75

1.35

2.29

0.356

0.457

4.00

3.90

3.80

6.20

6.00

5.80

5.00

4.90

4.80

0.10 MAX

0.05 NOM

3.81 REF

0.25

0.17

8°

0°

0.50

0.25

45°

COPLANARITY

0.10

1.04 REF

1.27 BSC

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

BOTTOM VIEW

TOP VIEW

0.51

0.31

1.65

1.25

Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-1)

Dimensions shown in millimeters

ADP7118ACPZN2.5-R7 Datasheet(PDF) 22 Page - Analog Devices

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