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STA306

3.2.2 High-Pass Filter Bypass

The STA306 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter

is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage

3.3 Configuration Register D (address 03h)

3.3.1 Binary Output Enable Registers

Each two-channel pair of outputs can be set to output a binary PWM stream. In this mode, output A

of a channel will be considered the positive output and output B is negative inverse. For example, setting C34BO

= 1 sets channels 3&4 to Binary Output (PWM) Mode.

3.3.2 Clock Output Select

The Clock Output Select register selects the frequency of the clock output pin relative to the PLL clock output.

The PLL clock runs at 2048fs for 32, 44.1, and 48kHz, at 1024fs for 88.2kHz and 96 kHz, and at 512fs for

176.4kHz and 192kHz.

3.3.3 Post-Scale Link

For multi-channel applications, the post-scale values can be linked to the value of channel 1 for ease of use and

update the values faster.

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

HPB

High-Pass Filter Bypass Bit. Setting of one bypasses internal AC

coupling digital high-pass filter

BIT

D7

D6

D5

D4

D3

D2

D1

D0

NAME

BQL

PSL

COS1

COS0

C78BO

C56BO

C34BO

C12BO

RST

0

0

1

000

0

0

BIT

R/W

RST

NAME

DESCRIPTION

0

R/W

0

C12BO

Channels 1&2, 3&4, 5&6 Binary Output Mode Enable Bits. A

setting of 0 indicates ordinary DDX tri-state output. A setting

of 1 indicates binary output mode.

1

R/W

0

C34BO

2

R/W

0

C56BO

3

R/W

0

C78BO

BIT

R/W

RST

NAME

DESCRIPTION

4

R/W

0

COS0

Clock Output Select

5

R/W

1

COS1

Clock Output Select

COS(1,0)

CKOUT Frequency

01

PLL Output/4

10

PLL Output/8

11

PLL Output/16

BIT

R/W

RST

NAME

DESCRIPTION

6

R/W

0

PSL

Post-Scale Link :0 – Each Channel uses individual Post-Scale value

1 - Each Channel uses Channel 1 Post-Scale value