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HT83072 Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HT83072 Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 21 page  HT83XXX Rev. 0.10 10 August 25, 2003 Preliminary Data Memory - RAM The data memory is designed with 80 ´8 bits. The data memory is further divided into two functional groups, namely, special function registers (00H~2AH) and gen- eral purpose user data memory (30H~7FH). Although most of them can be read or be written to, some are read only. The special function registers include an indirect ad- dressing register (R0:00H), memory pointer register (MP0:01H), accumulator (ACC:05H), program counter lower-order byte register (PCL:06H), table pointer (TBLP:07H), table higher-order byte register (TBLH:08H), status register (STATUS:0AH), interrupt control register 0 (INTC:0BH), timer counter 0 (TMR0:0DH), timer counter 0 control register (TMR0C:0EH), timer counter 1 (TMR1L:10H), timer counter 1 control register (TMR1C:11H), I/O registers (PA:12H), I/O control registers (PAC:13H), voice ROM address latch0[21:0] (LATCH0H:18H, LATCH0M:19H, LATCH0L:1AH), time base control bit EBTI (INTC.1), PWM control register (PWMCR:26H), PWM output (PWMD:28H), voice ROM latch data register (LATCHD:2AH). The general purpose data memory, addressed from 30H~7FH, is used for data and control information un- der instruction commands. The areas in the RAM can directly handle the arithmetic, logic, increment, decrement and rotate operations. Ex- cept some dedicated bits, each bit in the RAM can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through the Memory Pointer register 0 (MP0:01H). S p e c i a l P u r p o s e D A T A M E M O R Y 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 3 0 H 7 F H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 F H : U n u s e d . R e a d a s " 0 " M P 0 R 0 A C C P C L T B L P T B L H W D T S S T A T U S I N T C T M R 0 T M R 0 C T M R 1 T M R 1 C P A P A C L A T C H 0 H L A T C H 0 M L A T C H 0 L P W M D L A T C H D G e n e r a l P u r p o s e D a t a M e m o r y P W M C R RAM Mapping Address RAM Mapping Read/Write Description 00H R0 R/W Indirect addressing register 0 01H MP0 R/W Memory pointer 0 05H ACC R/W Accumulator 06H PCL R/W Program counter lower-order byte address 07H TBLP R/W Table pointer lower-order byte register 08H TBLH R Table higher-order byte content register 09H WDTS R/W Watchdog Timer option setting register |
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