ZL30791, ZL30795, ZL30793

Product Brief

4

Microsemi Confidential

•

Output jitter from Synth1 and Synth2 integer dividers is <0.3ps RMS

•

Output jitter from fractional dividers is <1ps RMS, many frequencies <0.5ps RMS

•

In CMOS mode, the HPOUTxN frequency can be an integer divisor of the HPOUTxP frequency

(Example 1: HPOUT3P 125MHz, HPOUT3N 25MHz. Example 2: HPOUT2P 25MHz, HPOUT2N 1Hz)

•

Outputs directly interface (DC coupled) with LVDS, LVPECL, HSTL, HCSL and CMOS components

•

Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN

•

Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components

•

Can produce PCIe clocks

•

Sophisticated output-to-output phase alignment

•

Per-synthesizer phase adjustment, 1ps resolution

•

Per-output phase adjustment

•

Per-output duty cycle / pulse width configuration

•

Per-output enable/disable

•

Per-output glitchless start/stop (stop high or low)

3.5

General-Purpose Output Clock Features

•

Two CMOS outputs from Synth0

•

Any frequency from 0.5Hz to 180MHz

•

Output jitter is typically 20-30ps

•

Useful for applications where the component or system receiving the signal has low bandwidth such as

a central timing IC

•

Can output a clock signal with embedded PPS (ePPS) (duty cycle distortion indicates PPS location)

3.6

Local Oscillator

•

Operates from a single TCXO or OCXO. Acceptable frequencies: 23.75MHz to 25MHz, 47.5MHz to

50MHz, 114.285MHz to 125MHz. Best jitter:

48MHz.

•

Very-low-jitter applications can connect a TCXO or OCXO (any frequency, any output jitter) as the

stability reference and a low-cost low-jitter XO as the jitter reference

•

This ability to have separate jitter and stability references greatly reduces the cost of the TCXO or

OCXO (no jitter requirement, no high-frequency-requirement) and allows reuse of already-qualified

TCXO and OCXO components

3.7

General Features

•

Automatic self-configuration at power-up from internal Flash memory

•

Input-to-output alignment <200ps with external feedback

•

Fast REF+SYNC locking for frequency and 1PPS phase alignment with lower-cost oscillator

•

Generates output SYNC signals: 1PPS (IEEE 1588), 2kHz or 8kHz (SONET/SDH) or other frequency

•

JESD204B clocking: device clock and SYSREF signal generation with skew adjustment

•

Internal compensation for local oscillator frequency error in DPLLs and input monitors, 1ppt resolution

•

Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency or

fractional output divider frequency with resolution better than 0.005ppt

•

Spread-spectrum modulation available in each fractional output divider (PCIe compliant)

•

Seven general-purpose I/O pins each with many possible status and control options

•

3.8

Evaluation Software

•

Simple, intuitive Windows-based graphical user interface

•

Supports all device features and register fields

•

Makes lab evaluation of the device quick and easy

•

Generates configuration scripts to be stored in internal Flash memory

•

Generates full or partial configuration scripts to be run on a system processor

•

Works with or without an evaluation board