LTC2430IGN datasheet(12/40 Pages) LINER

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LTC2430/LTC2431

24301f

Power-Up Sequence

The LTC2430/LTC2431 automatically enter an internal

reset state when the power supply voltage VCC drops

below approximately 2V. This feature guarantees the

integrity of the conversion result and of the serial interface

mode selection. (See the 2-wire I/O sections in the Serial

Interface Timing Modes section.)

When the VCC voltage rises above this critical threshold,

the LTC2430 or LTC2431 creates an internal power-on-

reset (POR) signal with a duration of approximately 1ms.

The POR signal clears all internal registers. Following the

POR signal, the converter starts a normal conversion

cycle and follows the succession of states described

above. The first conversion result following POR is accu-

rate within the specifications of the device if the power

supply voltage is restored within the operating range

(2.7V to 5.5V) before the end of the POR time interval.

Reference Voltage Range

The LTC2430/LTC2431 accept a differential external refer-

ence voltage. The absolute/common mode voltage speci-

fication for the REF+ and REF– pins covers the entire range

from GND to VCC. For correct converter operation, the

REF+ pin must always be more positive than the REF– pin.

The LTC2430/LTC2431 can accept a differential reference

voltage from 0.1V to VCC. The converter (LTC2430 or

LTC2431) output noise is determined by the thermal noise

of the front-end circuits, and, as such, its value in micro-

volts is nearly constant with reference voltage. A decrease

in reference voltage will not significantly improve the

converter’s effective resolution. On the other hand, a re-

duced reference voltage will improve the converter’s over-

all INL performance. A reduced reference voltage will also

improve the converter performance when operated with

an external conversion clock (external FO signal) at sub-

stantially higher output data rates.

Input Voltage Range

The analog input is truly differential with an absolute/com-

mon mode range for the IN+ and IN– input pins extending

from GND – 0.3V to VCC + 0.3V. Outside these limits, the

ESD protection devices begin to turn on and the errors due

to input leakage current increase rapidly. Within these lim-

its, the LTC2430 or LTC2431 converts the bipolar differen-

tial input signal, VIN = IN+ – IN–, from – FS = –0.5 • VREF

to +FS = 0.5 • VREF where VREF = REF+ – REF –. Outside this

range the converter indicates the overrange or the

underrange condition using distinct output codes.

Input signals applied to IN+ and IN– pins may extend by

300mV below ground and above VCC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN+ and IN– pins without affecting the performance

of the device. In the physical layout, it is important to main-

tain the parasitic capacitance of the connection between

these series resistors and the corresponding pins as low

as possible; therefore, the resistors should be located as

close as practical to the pins. In addition, series resistors

will introduce a temperature dependent offset error due to

the input leakage current. A 1nA input leakage current will

develop a 1ppm offset error on a 5k resistor if VREF = 5V.

This error has a very strong temperature dependency.

Output Data Format

The LTC2430/LTC2431 serial output data stream is 24 bits

long. The first 3 bits represent status information indicat-

ing the sign and conversion state. The next 21 bits are the

conversion result, MSB first. The third and fourth bits to-

gether are also used to indicate an underrange condition

(the differential input voltage is below – FS) or an overrange

condition (the differential input voltage is above + FS).

Bit 23 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 21 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW.

Bit 20 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 21 also

provides the underrange or overrange indication. If both

Bit 21 and Bit 20 are HIGH, the differential input voltage is

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