6

Application information

6.1

External capacitors

The ST732 voltage regulator requires external capacitors to ensure the control loop stability. These capacitors

must be selected to meet the requirements of minimum capacitance and equivalent series resistance defined in

the following chapters. Input and output capacitors should be located as close as possible to the relevant pins.

Input capacitor

An input capacitor, whose minimum value is 0.1 μF, must be placed as close as possible to the input in of the

device and returned to a clean analog ground. A good quality, low-ESR ceramic capacitor is suggested. It helps

to ensure stability of the control loop, reduces the effects of inductive sources and improves ripple rejection.

Values, which are higher than 0.1 µF, are suggested in case of fast load transients in the application. There is no

maximum limit to the output capacitance.

Output capacitor

The ST732 requires a capacitor connected on its output, to keep the control loop stable and reduce the risk of

ringing and oscillations. The control loop is designed to be stable with any good quality ceramic capacitor (such

as X5R/X7R types) with a minimum value of 0.47 µF and equivalent series resistance in the [5 – 500 mΩ] range.

It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable region

over the full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance

and ESR variations must be taken into account in the design phase to ensure the device works in the expected

stability region.

There is no maximum limit to the output capacitance, provided that the above conditions are satisfied.

6.2

Power dissipation

A proper PCB design is recommended, to ensure that the device internal junction temperature is kept below 125

°C, in all operating conditions. The thermal energy, generated by the device, flows from the die surface to the

PCB copper area through the package leads. The PCB copper area acts as a heat sink. The footprint copper

pads should be as wider as possible to spread and dissipate heat to the surrounding environment. Thermal

micro-vias to the inner or backside copper layers improve the overall thermal performance of the device.

The power dissipation of the LDO depends on the input voltage, output voltage and output current, and is given

by:

PD= VIN−VOUT IOUT

(1)

The junction temperature of the device is:

TJ_MAX=TA+RtℎJA×PD

(2)

resistance junction-to-ambient.

With the above equation it is possible to calculate the allowable maximum power dissipation, therefore the

maximum load current for a certain voltage drop. Appropriate de-rating of the operating condition can be applied

accordingly.

6.3

Protection features

Current limit

Due to the wide input voltage range, high power dissipation could occur in case of damaged/shorted load. For this

reason the ST732 embeds an SOA protection-current limit circuit, which acts in case of overload or short-circuit

on the output, clamping the load current to a safe value.

power is always kept under control.

The non-constant current limit characteristic shown in Figure 15. Current limit vs. temperature should be taken

into account to calculate the maximum load current the device can supply for a certain dropout voltage.

Normal operation is restored if the overload disappears, but prolonged operation in current limit may lead to high

power dissipation inside the LDO and subsequently to thermal shutdown.

ST732

Application information

DS12561 - Rev 3

page 7/21