3 / 13 page
CY28159
Document #: 38-07118 Rev. **
Page 3 of 13
Test Load Configuration
The following shows test load configurations for the different Host Clock Outputs.(MULTsel1 = 0, MULTsel0 =1
Table 2. Group Offset Specifications
Group
Offset
Comments
CPU to 3V33
No requirement
CPU to REF
No requirement
Table 3. Group Limits and Parameters (Applicable to all
settings: Sel133/100#=x)
Output Name
Max Load
CPU[(0:7)#]
See Figure 1
REF
20 pF
3V33
30 pF
CPUT
MULTSEL
T
PCB
T
PCB
CPUT#
33Ω
33Ω
Measurement Point
49.9Ω
49.9Ω
2pF
Measurement Point
2pF
221Ω
VDD
Figure 1. 0.7V Test Load Termination
CLOAD
Probe
Output Under Test
Figure 2. Lumped Load Termination
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
