Advanced Clock Drivers Devices

4

Freescale Semiconductor

MPC9850

OPERATION INFORMATION

Output Frequency Configuration

The MPC9850 was designed to provide the commonly

used frequencies in PowerQUICC, PowerPC and other

microprocessor systems. Table 3 lists the configuration

values that will generate those common frequencies. The

MPC9850 can generate numerous other frequencies that

may be useful in specific applications. The output frequency

following equation.

This calculation is valid for all values of N from 8 to 126.

Note that N = 15 is a modified case of the configuration inputs

CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to

00111 or 7.

Crystal Input Operation

TBD

Power-Up and MR Operation

Figure 2 defines the release time and the minimum pulse

length for MR pin. The MR release time is based upon the

Table 11 for actual parameter values. The MPC9850 may be

configured after release of reset and the outputs will be stable

for use after lock indication is obtained.

Figure 2. MR Operation

Power Supply Bypassing

The MPC9850 is a mixed analog/digital product. The

architecture of the MPC9850 supports low noise signal

operation at high frequencies. In order to maintain its superior

high-frequency ceramic capacitors connected to GND. If the

spectral frequencies of the internally generated switching

noise on the supply pins cross the series resonant point of an

individual bypass capacitor, its overall impedance begins to

look inductive and thus increases with increasing frequency.

The parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the noise bandwidth.

MR

MPC9850

0.1

µF

22

µF

0.1

µF

15

Ω