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AT24CSW04X Datasheet(PDF) 21 Page - Microchip Technology |
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AT24CSW04X Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 43 page  7.4 Write Cycle Timing The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that begins the internal write cycle to the Start condition of the first device address byte sent to the AT24CSW04X/AT24CSW08X that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement. During the internally self-timed write cycle, any attempts to read from or write to the memory array will not be processed. Figure 7-4. Write Cycle Timing t WR Stop Condition Start Condition Data Word n ACK D0 SDA Stop Condition SCL 8 9 ACK First Acknowledge from the device to a valid device address sequence after write cycle is initiated. The minimum t WR can only be determined through the use of an ACK Polling routine. 9 AT24CSW04X/AT24CSW08X Write Operations © 2020-2021 Microchip Technology Inc. and its subsidiaries Datasheet DS20006426B-page 21 |
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