 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT25QL128A Datasheet(PDF) 13 Page - Dialog Semiconductor |
|
|
|||||||||||||||||||||||||||||
AT25QL128A Datasheet(HTML) 13 Page - Dialog Semiconductor |
|
|
13 / 84 page  12 AT25QL128A DS-AT25QL128A–129E–01-2021 7 Status Register The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the device’s write protection features and the Quad SPI setting. Write access to the Status Register is controlled in some cases by the WP pin. 7.1 Busy BUSY is a read-only bit in the status register (S0) that is set to 1 when the device is executing a Page Program, Erase, Write Status Register, or Write Security Register instruction. During this time, the device ignores further instructions, except for the Read Status Register and Erase / Program Suspend instruction (see tW, tPP, tSE, tBE1, tBE2, and tCE in Section 9.6, AC Electrical Characteristics, on page 73). When the Program, Erase, Write Status Register, or Write Security Register instruction has completed, the BUSY bit is cleared to a 0 state, indicating the device is ready for further instructions. Other exceptions are the Enable Reset (66h) and Reset (99h) commands. Even if the BUSY bit is active (1), the device accepts and executes a RESET command from the host system. The host system must wait for the BUSY bit to become inactive (0) before sending the RESET command. If the device receives a RESET command during an ERASE or in Program mode, memory corruption can occur. See Section 8.34, Enable Reset (66h) and Reset (99h) for more information. 7.2 Write Enable Latch (WEL) Write Enable Latch (WEL) is a read-only bit in the status register (S1) that is set to a 1 after executing a Write Enable instruction. It is cleared to 0 when device is write-disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Erase and Write Status Register. 7.3 Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide write protection control and status. Block protect bits can be set using the Write Status Register Instruction (see tW in Section 9.6, AC Electrical Characteristics, on page 73). All, none, or a portion of the memory array can be protected from Program and Erase instructions (see Table 7-2, on page 14, and Table 7-3, on page 15). The S7 S6 S5 S4 S3 S2 S1 S0 SRP SEC TB BP2 BP1 BP0 WEL BUSY Status Register Protect 0 (Non- Volatile) Sector Protect (Non- Volatile) Top/Bottom Write Protect (Non- Volatile) Block Protect (Non- Volatile) Block Protect (Non- Volatile) Block Protect (Non- Volatile) Write Enable Latch Erase or Write in Progress S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP (R) (R) (R) (R) QE SRP1 Suspend Status Complement Protect (Non- Volatile) Reserved Reserved Reserved Reserved Quad Enable (Non- Volatile) Register Protect 1 (Non- Volatile) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
