AT25QL321 datasheet(5/79 Pages) DIALOG

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AT25QL321

DS-25QL321–131C–5/2017

During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max).

All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL.

Table 1-1.

Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CHIP SELECT

When this input signal is high, the device is deselected and serial data output pins are at

high impedance. Unless an internal program, erase or write status register cycle is in

progress, the device will be in the standby power mode (this is not the deep power down

mode). Driving Chip Select (CS) low enables the device, placing it in the active power

mode. After power-up, a falling edge on Chip Select (CS) is required prior to the start of

any instruction.

Low

Input

SCK

SERIAL CLOCK

This input signal provides the timing for the serial interface. Instructions, addresses, or

data present at serial data input are latched on the rising edge of Serial Clock (SCK).

Data are shifted out on the falling edge of the Serial Clock (SCK).

Input

SI (I/O0)

SERIAL INPUT

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched in on

the rising edge of SCK.

With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output

pin (I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-0) to be

clocked in on every falling edge of SCK

To maintain consistency with the SPI nomenclature, the SI (I/O0) pin is referenced as the

SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it is

referenced as I/O0.

Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted).

Input/Output

SO (I/O1)

SERIAL OUTPUT

The SO pin is used to shift data out from the device. Data on the SO pin is always

clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in

conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every

falling edge of SCK

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin is referenced as

the SO pin unless specifically addressing the Dual-I/O modes in which case it is

referenced as I/O1. The SO pin is in a high-impedance state whenever the device is

deselected (CS is deasserted).

Input/Output

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