c) JU3 (2-3)—Demux parallel mode selected if

JU2 is pulled high

d) JU4 (2-3)—Two’s-complement output selected

e) JU5 (1-2)—Noninverted DCLKP selected

f) JU6 (2-3)—Noninverted DCLKN selected

g) JU7 (3-4)—Internal reference enabled

2)

Connect the clock signal generator to the SMA

connector labeled CLK.

3)

Connect the analog input signal generator to the

SMA connector labeled INP.

4)

Connect the logic analyzer’s high-speed state card

probe connectors to header J1 (CMOS-compatible

5)

Connect a 1.8V, 1A power supply to AVCC.

Connect the ground terminal of this supply to the

GND pad closest to the AVCC pad.

6)

Connect a 3.3V, 500mA power supply to CVCC.

Connect the ground terminal of this supply to the

GND pad closest to the CVCC pad.

7)

Connect a 1.8V, 500mA power supply to BVCC.

Connect the ground terminal of this supply to the

GND pad closest to the BVCC pad.

8)

Connect a 1.8V, 1A power supply to OVCC.

Connect the ground terminal of this supply to the

GND pad closest to the OVCC pad.

9)

Turn on all the power supplies.

10) Enable the signal generators. Set the clock signal

amplitude. Set the analog input signal generato to

output the desired frequency with an amplitude

tors should be synchronized.

11) Enable the logic analyzer.

12) Collect data using the logic analyzer.

Detailed Description

The MAX19541/MAX19542 EV kits are fully assembled

and tested PCBs that contain all the components nec-

essary

to

evaluate

the

performance

of

the

MAX19541/MAX19542. The MAX19541/MAX19542 can

170MHz.

The MAX19541/MAX19542 accept differential inputs.

Applications that only have a single-ended signal source

available can use the on-board transformer (T2) to con-

vert a single-ended signal to a differential signal.

Output buffers (U3 and U4) buffer the digital output sig-

nals of the MAX19541/MAX19542 to higher capacitive

load signals that can be captured by a wide variety of

logic analyzers. The buffered CMOS outputs can be

accessed at headers J1 and J2.

Each EV kit is designed as a four-layer PCB to optimize

the performance of the MAX19541/MAX19542. Separate

analog, digital, clock, and buffer power planes minimize

noise coupling between analog and digital signals; 50

Ω

coplanar transmission lines are used for analog and

clock inputs. The trace lengths of the 50

Ω CMOS lines

are matched to within a few thousandths of an inch to

minimize layout-dependent delays.

Power Supplies

The MAX19541/MAX19542 EV kits require separate

analog, digital, clock, and buffer power supplies for

best performance. Two separated 1.8V power supplies

are used to power the analog and digital portions of the

MAX19541/MAX19542. The on-board clock circuitry is

powered by another 3.3V power supply, and a 1.8V

power supply is used to power the output buffers (U3

and U4) on the EV kits.

Clock

The MAX19541/MAX19542 require a differential clock

signal. However, if only a single-ended clock signal

source is available, the EV kit’s on-board level transla-

tor helps to convert a single-ended clock to the

required differential signal. An on-board clock-shaping

circuit generates a differential clock signal from an AC-

coupled sine-wave signal applied to the clock input

SMA connector CLK. The input signal amplitude should

should not exceed 170MHz. The frequency of the sinu-

soidal input clock signal determines the sampling fre-

(U2) processes the input signal to generate the

required clock signal.

Clock Divider

The MAX19541/MAX19542 feature an internal divide-

by-two clock divider. Use jumper JU1 to enable/disable

MAX19541/MAX19542 Evaluation Kits

_______________________________________________________________________________________

3

SHUNT

POSITION

MAX19541/MAX19542

CLKDIV PIN

DESCRIPTION

1-2*

Connected to AVCC

Clock signal

divided by 1

2-3

Connected to GND

Clock signal

divided by 2

(JU1)

*Default position.