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ADP5065ACBZ-1-R7 Datasheet(PDF) 29 Page - Analog Devices

Part # ADP5065ACBZ-1-R7
Description  Fast Charge Battery Manager with Power Path and USB Compatibility
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP5065ACBZ-1-R7 Datasheet(HTML) 29 Page - Analog Devices

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Data Sheet
ADP5065
Rev. D | Page 29 of 40
Bit No.
Mnemonic
Access
Default
Description
[2:0]
VWEAK[2:0]
R/W
011 = 3.0 V
Weak battery voltage rising threshold.
000 = 2.7 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.1 V.
101 = 3.2 V.
110 = 3.3 V.
111 = 3.4 V.
Table 21. Timer Settings, Register Address 0x06 Bit Descriptions
Bit No.
Mnemonic
Access
Default
Description
[7:6]
Not used
5
EN_TEND
R/W
0
When low, this bit disables the charge complete timer (tEND), and a 31
ms deglitch timer remains on this function.
4
EN_CHG_TIMER
R/W
1
When high, the trickle/fast charge timer is enabled.
3
CHG_TMR_PERIOD
R/W
1
Trickle/fast charge timer period.
0 = 30 sec/300 minutes.
1 = 60 sec/600 minutes.
2
EN_WD
R/W
0
When high, the watchdog timer safety timer is enabled.
When low, the watchdog timer is disabled even when BAT_SNS
exceeds VDEAD.
1
WD PERIOD
R/W
0
Watchdog safety timer period.
0 = 32 sec/40 minutes.
1 = 64 sec/40 minutes.
0
RESET_WD
W
0
High resets the watchdog safety timer. Bit is reset automatically.
Table 22. Functional Settings1, Register Address 0x07 Bit Descriptions
Bit No.
Mnemonic
Access
Default
Description
7
EN_JEITA
R/W
0
When low, this bit disables the JEITA Li-Ion temperature battery
charging specification.
6
DIS_IPK_SD
R/W
1
When high, this bit disables the automatic shutdown of the device if
four peak inductor current limits are reached in succession. In
addition, when high, it only flags the Status Bit IPK_STAT.
5
EN_BMON
R/W
0
When high, the battery monitor is enabled even when the voltage at
the VINx pins is below VVIN_OK.
4
EN_THR
R/W
0
When high, the THR current source is enabled even when the
voltage at the VINx pins is below VVIN_OK.
3
Not used
R/W
0
2
EN_EOC
R/W
1
When high, end of charge is allowed.
1
EN_TRK
R/W
1
When low, trickle charger is disabled and the dc-to-dc converter is
enabled.
0
EN_CHG
R/W
1
When low, the dc-to-dc converter is disabled.
Table 23. Functional Settings2, Register Address 0x08 Bit Descriptions
Bit No.
Mnemonic
Access
Default
Description
[7:0]
Not used
R/W
Table 24. Interrupt Enable, Register Address 0x09 Bit Descriptions
Bit No.
Mnemonic
Access
Default
Description
7
EN_IND_PEAK_INT
R/W
0
When high, the inductor peak current-limit interrupt is allowed.
6
EN_THERM_LIM_INT
R/W
0
When high, the isothermal charging interrupt is allowed.
5
EN_WD_INT
R/W
0
When high, the watchdog alarm interrupt is allowed.
4
EN_TSD_INT
R/W
0
When high, the overtemperature interrupt is allowed.
3
EN_THR_INT
R/W
0
When high, the THR temperature thresholds interrupt is allowed.



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