MSM7524 datasheet(5/21 Pages) OKI

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¡ Semiconductor

MSM7524

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Analog ground, 0 V.

This pin should be common with DG (pin 23) at the system ground point.

Pin No.

Name

I/O

8AG

—

Power supply, +5 V.

9VDD

—

Power down control.

When digital "1" is applied to

PON, the whole circuitry on chip falls

into the power down mode.

This pin is pulled-up to digit "1" internaly.

PON

X1 and X2 are connected to a 3.579545 MHz crystal to generate a

crystal clock for the chip.

If required to use an external clock, X1 should be left open and X2

should be connected to the external clock source via a capacitor

of 100 pF.

3.579545 MHz clock output.

CLKO

External processor interface clock input.

During "WRITE" mode, the data on D4 to D1 pins are written into the

internal register at the falling edge of SCLK. During "READ" mode,

the output data from the internal register appears on D4 to D1 pins

at the rising edge of SCLK.

SCLK is not required to be a periodic clock pulse stream. SCLK is

internally pulled-down to digital "0".

SCLK

Chip select.

When

CS is on digital "0", "READ" and "WRITE" operations become

possible.

CS is internally pulled-down.

Address data input.

When digital "1" is applied to AD0, data writing into the control

When digital "0" is applied to, data writing into the DTMF tone transmit

become possible. AD0 is internally pulled-down.

ADO

"READ" and "WRITE" control signal input.

"READ" or "WRITE" operation becomes possible during digital "1" or "0",

respectively.

W is internally pulled-down to digital "0".

I/O

4-bit micro-processor interface bus.

All pins are internally pulled-down.

Description

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