VSC8658 datasheet(36/95 Pages) MICROSEMI

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Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

5.2.1

Mode Control

The device register at memory address 0 controls several aspects of VSC8658 functionality. The

following table shows the available bit settings in this register and what they control.

Interrupt mask

Interrupt status

MAC interface auto-negotiation control and status

Auxiliary control and status

LED mode select

LED behavior

Extended register page access

Table 11 •

Mode Control, Address 0 (0x00)

Bit

Name

Access

Description

Default

Software reset

R/W

This is a self-clearing bit that restores all

serial management interface (SMI) registers

to their default state, except for sticky and

super sticky bits.

1 = Reset asserted.

0 = Reset de-asserted.

You must wait 4 µs after setting this bit to

initiate another SMI register access.

Loopback

R/W

1 = Loopback enabled.

0 = Loopback disabled.

When loop back is enabled, the device

functions at the current speed setting and

with the current duplex mode setting (bit 8 of

this register).

LSB for speed

selection

R/W

See bit 6 below.

Auto-negotiation

enable

R/W

1 = Auto-negotiation enabled.

0 = Auto-negotiation disabled.

Power-down

R/W

1 = Power-down enabled.

Isolate

R/W

1 = Disable MAC interface outputs and ignore

MAC interface inputs.

Restart auto-

negotiation

R/W

This is a self-clearing bit.

1 = Restart auto-negotiation on media

interface.

Duplex

R/W

1 = Full-duplex.

0 = Half-duplex.

Collision test enable

R/W

1 = Collision test enabled.

6, 13

Forced speed

selection

R/W

MSB = bit 6, LSB = bit 13.

00 = 10 Mbps.

01 = 100 Mbps.

10 = 1000 Mbps.

11 = Reserved.

Table 10 •

Main Registers (continued)

VSC8658 Datasheet(PDF) 36 Page - Microsemi Corporation

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