Connection Diagram

8 Lead LLP Surface Mount Package (SD)

20086850

Top View

See NS Package Number SDC08A

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output Voltage*

Grade

Order Information

Supplied as:

8 Lead LLP

1.0

STD

LP3878SD-1.0

1000 Units on Tape and Reel

1.0

STD

LP3878SDX-1.0

4500 Units on Tape and Reel

* For other voltages between 1.0V and 1.2V, contact National Semiconductor sales office.

Pin Description

PIN

NAME

APPLICATION INFORMATION

1

BYPASS

Optional low noise feature. A small value capacitor connected between

BYPASS and GROUND lowers output noise voltage level (100pF -

10nF).

2

N/C

DO NOT CONNECT. This pin is used for post package test and should

be left floating.

3

GROUND

Device ground.

4

INPUT

Input source voltage.

5

OUTPUT

Regulated output voltage.

6

SENSE

Remote sense. Tie directly to output or remotely at point of load for best

regulation.

7

N/C

No internal connection.

8

SHUTDOWN

Enabled above turn-on threshold voltage. Pull to ground to disable.

LLP

DAP

SUBSTRATE

The exposed die attach pad should be connected to a thermal pad at

ground potential. For additional information on using National

Semiconductor’s No Pull Back LLP package, please refer to LLP

application note AN-1187.

www.national.com

3