UT54ACS164245SWC datasheet(2/14 Pages) AEROFLEX

2 / 14 page

PINOUTS

POWER TABLE1

NOTE:

1. V DD2 cannot be tied to V SS while power is applied to VDD1.

Control signals DIRx and OEx are 5 volt tolerant inputs. When

VDD2 is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can

be applied to all control inputs. For proper operation connect

power to all VDD and ground all V SS pins (i.e., no floating VDD

or VSS input pins). Tie unused inputs to VSS. If VDD1 and

VDD2 are not powered up together, then VDD2 should be pow-

ered up first for proper control of OE and DIR. Until VDD2

reaches 2.75V + 5%, control of the outputs byOE and DIR can-

not be guaranteed. During operation of the part, after power up,

insure VDD1 > VDD2. Tie unused inputs to VSS.

DIR1

1B1

1B2

VSS

1B3

1B4

VDD1

OE1

1A1

1A2

VSS

1A3

VDD2

1B5

1A5

1A4

1B6

1A6

VSS

48-Lead Flatpack

Top View

1B7

1B8

2B1

2B2

VSS

2B3

2B4

VDD1

2B5

2B6

VSS

2B7

2B8

DIR2

1A7

1A8

2A1

2A2

VSS

2A4

VDD2

2A3

2A5

2A6

VSS

2A7

2A8

OE2

Port B

Port A

OPERATION

5 Volts

3.3 Volts

Voltage Translator

5 Volts

Non Translating

3.3 Volts

Non Translating

VSS

Cold Spare

VSS

3.3V or 5V

Port B Cold Spare

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