1

PS8419C

01/12/05

1

2

3

4

CLK_OUT

CLK_IN

GND

FB_IN

8

7

6

5

AGND

S

Product Pin Configuration

Logic Block Diagram

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PI6C2401

Product Features

• High-Performance Phase-Locked-Loop Clock Distribution for

Networking, ATM, 100/134 MHz Registered DIMM Synchro-

nous DRAM modules for server/workstation/PC applications

• Zero Input-to-Output delay

• Lowjitter:Cycle-to-Cyclejitter ±100psmax.

• On-chip series damping resistor at clock output drivers

for low noise and EMI reduction

• Packaged in Plastic 8-pin SOIC Package (W)

Pb-free and Green Available

• Wide range of Clock Frequencies

Phase-Locked Loop Clock Driver

Product Description

The PI6C2401 features a low-skew, low-jitter, phase-locked loop

(PLL) clock driver. By connecting the feedback CLK_OUT output

to the feedback FB_IN input, the propagation delay from the

CLK_IN input to any clock output will be nearly zero.

Application

If the system designer needs more than 16 outputs with the features

just described, using two or more zero-delay buffers such as

PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-

to-device skew introduced can significantly reduce

the performance. Pericom recommends the use of a zero-delay

buffer and an eighteen output non-zero-delay buffer . As shown in

Figure 1, this combination produces a zero-delay buffer with all the

signal characteristics of the original zero-delay buffer, but with as

many outputs as the non-zero-delay buffer part. For example, when

combined with an eighteen output non-zero delay buffer, a system

designer can create a seventeen-output zero-delay buffer.

Figure 1. This Combination Provides Zero-Delay Between

the Reference Clocks Signal and 17 Outputs

17

Zero Delay

Buffer

PI6C2401

Reference

Clock

Signal

CLK_OUT

Feedback

18 Output

Non-Zero

Delay

Buffer

Se

c

r

u

o

S

t

u

p

t

u

On

w

o

d

t

u

h

S

L

L

P

1L

L

PN

0N

I

_

K

L

CY

Control Input

CLK_IN

FB_IN

S

PLL

CLK_OUT

8-Pin

W