MAX15053_V01 datasheet(13/21 Pages) MAXIM

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set to 0.3). In addition, the peak inductor current, IL_PK,

must always be below the minimum high-side current-

limit value, IHSCL, and the inductor saturation current

rating, IL_SAT.

Ensure that the following relationship is satisfied:

(

)

L_PK

LOAD

HSCL, L_SAT

min I

+∆ <

Input Capacitor Selection

The input capacitor reduces the peak current drawn from

the input power supply and reduces switching noise in the

device. The total input capacitance must be equal to or

greater than the value given by the following equation to

keep the input ripple voltage within the specification and

minimize the high-frequency ripple current being fed back

to the input source:

LOAD

OUT

IN_RIPPLE

×∆

where DVIN_RIPPLE is the maximum-allowed input ripple

voltage across the input capacitors and is recommended

to be less than 2% of the minimum input voltage, fSW is

the switching frequency (1MHz), and ILOAD is the output

load. The impedance of the input capacitor at the switch-

ing frequency should be less than that of the input source

so high-frequency switching currents do not pass through

the input source, but are instead shunted through the

input capacitor.

The input capacitor must meet the ripple current require-

ment imposed by the switching currents. The RMS input

ripple current is given by:

(

)

OUT

RIPPLE

LOAD



−





where IRIPPLE is the input RMS ripple current.

Output Capacitor Selection

The key selection parameters for the output capacitor are

capacitance, ESR, ESL, and voltage rating. The param-

eters affect the overall stability, output ripple voltage, and

transient response of the DC-DC converter. The output

ripple occurs due to variations in the charge stored in

the output capacitor, the voltage drop due to the capaci-

tor’s ESR, and the voltage drop due to the capacitor’s

Figure 1. Peak Current-Mode Regulator Transfer Model

VCOMP

IOUT

COMPARATOR

COMP

VCOMP

VFB

ROUT

gMV

VIN

POWER MODULATOR

OUTPUT FILTER

AND LOAD

NOTE: THE GMOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF

THE INDUCTOR, IL, INJECTED INTO THE OUTPUT LOAD, IOUT, e.g., IL = IOUT.

THIS CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER

STATE CIRCUITRY SHOWN WITHIN THE BOXED AREA.

*NOTE: CFF IS OPTIONAL AND DESIGNED TO EXTEND THE

REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE

MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS.

ERROR AMPLIFIER

FEEDBACK

DIVIDER

SLOPE

COMPENSATION

RAMP

gMC

DCR

QLS

VOUT

QHS

IOUT

ESR

COUT

RLOAD

REF

ROUT = 10AVEA(dB)/20/gMV

*CFF

GMOD

PWM

CONTROL

LOGIC

MAX15053

High-Efficiency, 2A, Current-Mode Synchronous,

Step-Down Switching Regulator

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