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SP3085 Datasheet(PDF) 5 Page - Shanghai Leiditech Electronic Technology Co., Ltd |
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SP3085 Datasheet(HTML) 5 Page - Shanghai Leiditech Electronic Technology Co., Ltd |
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5 / 10 page ![]() Transmission characteristics Unless otherwise specified, V DD = 5V 5% and Tamb = 25 °C Features slope limiting Drive input to Output tDPLH RDIFF=50Ω, CL1=CL2=100pF(3)(6) 250 720 1000 ns Drive input to Output tDPHL RDIFF=50Ω, CL1=CL2=100pF(3)(6) 250 720 1000 ns |tDPLH-tDPHL| tDSKEW -3 ±100 ns Drive up and down Time tDR,tDF 200 530 750 ns Maximum data transfer rate fMAX 500 kbps Drive enable delay tDZH CL=100pF,S2 CLOSED(4)(7) 2500 ns Drive enable delay tDZL CL=100pF,S1 CLOSED(4)(7) 2500 ns Drive shutdown delay tDLZ CL=15pF,S1 CLOSED(4)(7) 100 ns Drive shutdown delay tDHZ CL=15pF,S2 CLOSED(4)(7) 100 ns Receiver input and output Delay tRPLH | VID|≥2.0V Rise and fall time ≤ 15ns(5)(8) 127 200 ns Receiver input and output Delay tRPHL 127 200 ns |tRPLH-tRPHL| tRSKD 3 ±30 ns Receiver enable delay tRZL CL=100pF,S1 CLOSED(2)(9) 20 50 ns Receiver enable delay tRZH CL=100pF,S2 CLOSED(2)(9) 20 50 ns Receiver shutdown delay tRLZ CL=100pF,S1 CLOSED(2)(9) 20 50 ns Receiver shutdown delay tRHZ CL=100pF,S2 CLOSED(2)(9) 20 50 ns PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SP3085 www.leiditech.com Rev 1.6 :01.01.2022 5/10 RDIFF=50Ω, CL1=CL2=100pF(3)(6) RDIFF=50Ω, CL1=CL2=100pF(3)(6) | VID|≥2.0V Rise and fall time ≤ 15ns(5)(8) Note: (1) The test circuit is shown in Figure 1 (2) The test line is shown in Figure 2 (3) The test circuit is shown in Figure 3 (4) The test circuit is shown in Figure 4 (5) The test line is shown in Figure 5 (6) The test line is shown in Figure 6 (7) The test circuit is shown in Figure 7 (8) The test circuit is shown in Figure 8 (9) The test line is shown in Figure 9 |
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